Cml output drivers

Figure 6b: CML Transmitter output waveforms for K bit pattern The Current Mode Logic (CML) output driver stage comprises a stack of four driver segments and is controlled by a 7-bit binary weighted tap. Each segment is in turn grouped in cluster of 32 unit driver fingers and the switching within the driver segment happens in. The output swing is subjected to the CML tail current source, and the voltage efficiency is limited by the saturation voltage (Vtail) of the tail current source. It can be shown that the voltage efficiency of CML driver is given by 3ISRT/VDD. The RLM of the CML driver can be limited by distortion that occurs when the tail transistor enters.  · Where the LVDS output drivers are used in a mixed parallel-serial interface in the ADCs that ADI offers, CML drivers are employed in the complex serial interface defined by the JESD standard. In this case, there is typically one serial lane (or data output pair) per ADC, so one of the benefits is that the number of I/O required is greatly reduced.

Where the LVDS output drivers are used in a mixed parallel-serial interface in the ADCs that ADI offers, CML drivers are employed in the complex serial interface defined by the JESD standard. In this case, there is typically one serial lane (or data output pair) per ADC, so one of the benefits is that the number of I/O required is greatly reduced. The CML output driver is employed in JESD interfaces that are being used on the latest converters. Utilizing CML drivers with serialized JESD interfaces allows data rates on the converter outputs to go up to 12 Gbps (with the current revision of the specification JESDB). CML Output to LVDS Input The HOTLink II CML outputs are V CC referenced and as such will be too high to interface directly to standard LVDS inputs, AC-coupling will be necessary to interface between HOTLink II outputs and LVDS inputs. The TIA/EIA spec defines the maximum differential input as mV, though most LVDS implementations will operate correctly with differ-ential input swings much higher than this.

Each output driver must be externally terminated as shown in the Input/Output Termination Recommendations section. The output voltage swing, internal. The VML driver outputs a high-swing signal and consumes less power than a current-mode-logic output stage current of the CML driver can be expressed as. Figure 6 Current-Mode Logic (CML) Driver. Output Driver Rise-Time. The rise time of an output driver must be carefully chosen to avoid excessive ISI.